GlobalWellPCBPCB & PCBA Manufacturing

PCB Impedance Calculator

Estimate single-ended, uncoated microstrip impedance—or solve trace width for a target. See the model, geometry limits and assumptions before using the result.

QUASI-STATIC MICROSTRIPHammerstad–Jensen

One trace. One reference plane.
No solder mask or differential coupling.

Set the geometry. See the estimate.

All dimensional inputs share one unit. Use finished copper and pressed dielectric height—not total board thickness.

This tool needs JavaScript. Until it loads, no calculated or screened result is available.

Your inputs

Updates as you edit
Changing units converts existing dimensions.
Relative Dk for the intended construction; 1–20.
Finished conductor width.
Used only in inverse-width mode.
Trace underside to reference-plane surface.
Finished copper; 0 models an ideal thin sheet.

Calculated locally in this browser. No inputs are uploaded.

Supported structure: one uncoated surface microstrip over a continuous plane. Differential pairs, coplanar lines, stripline, offset layers and solder-mask coatings are deliberately not calculated by this model.

The model is part of the result.

This page implements the quasi-static Hammerstad–Jensen microstrip relationship, with its finite-thickness width correction. It is an equation-based estimate, not a two-dimensional field solution or a measured board result. Equation reference · Implementation cross-check

The inverse tool bisects the same model’s permitted width interval. It does not switch to a different approximation to force a target to fit.

Inputs describe the finished cross-section

H is the distance from the underside of the trace to the top of the reference plane. T is the finished conductor thickness. W is the rectangular conductor width used by this model. All three must use the same length unit.

Deliberately bounded input envelope

This implementation accepts 1 ≤ εr ≤ 20, 0.1 ≤ W/H ≤ 10, T/H ≤ 0.25 and T/W ≤ 0.5. These are tool guards, not a promised percentage error or fabrication capability. Unsupported geometry produces an error, not an extrapolated answer.

What is not modeled

Frequency dispersion, dielectric anisotropy, copper roughness, trapezoidal etching, mask, neighboring copper, finite plane edges, via transitions and pair coupling are excluded. Use a fabrication-approved solver and stackup for release. Displayed decimals describe numerical resolution, not board tolerance.

Inspect the implemented equations
u = W/H; v = T/H
Δu₁ = (v/π) ln[1 + (4e/v) tanh²(√(6.517u))]
Δuᵣ = Δu₁ [1 + sech(√(εr−1))] / 2
uᵣ = u + Δuᵣ; u₁ = u + Δu₁

F(u) = 6 + (2π−6) exp[−(30.666/u)^0.7528]
Zair(u) = η₀/(2π) ln[F(u)/u + √(1+(2/u)²)]
a(u) = 1 + ln[(u⁴+(u/52)²)/(u⁴+0.432)]/49
       + ln[1+(u/18.1)³]/18.7
b = 0.564 [(εr−0.9)/(εr+3)]^0.053
εe(u) = (εr+1)/2 + (εr−1)/2 · (1+10/u)^(−a·b)

Z₀ = Zair(uᵣ)/√εe(uᵣ)
εeff = εe(uᵣ) [Zair(u₁)/Zair(uᵣ)]²
For T=0, Δu₁ = Δuᵣ = 0.
η₀ = 376.730313668 Ω (rounded reference)

Questions before
you use the result.

Know what the tool answers—and what still needs engineering review.

Can I calculate a 100 Ω differential pair here?

No. This release calculates only a single uncoated microstrip. Doubling its isolated-line impedance is not a coupled-pair calculation. Use a suitable differential field solver.

Should H be the entire 1.6 mm board thickness?

Only when that is the actual trace-to-reference-plane dielectric separation. On a multilayer board H is usually the distance to the relevant plane, not the whole board.

Is the inverse width ready for manufacturing?

No. Approve the actual stackup, mask, etch profile and tolerances with the fabricator. The inverse result solves the same idealized model, not the complete manufactured geometry.

Technical references & data basis

Check the linked manufacturer data and calculation references when using your results. Confirm the exact material grade and applicable document revision before production.

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