BGA & Fine-Pitch Design Guidelines
Connect the package drawing, board construction and assembly process before committing to a dense layout. A small pitch is a design input—not a complete manufacturing specification.
- Package to board
Ball map, land pattern and escape routing
- Paste to joint
Apertures, board surface and thermal process
- Joint to evidence
Hidden-joint inspection and electrical tests
Start with the exact package—not a generic “BGA” rule.
Package guidance differs across BGA, wafer-level and bottom-terminated devices. Select the application note and drawing for the actual manufacturer part number, including its package option, rather than copying a footprint from a similarly named component.
The review should connect the electrical escape strategy to the finished solderable surface and the proposed assembly process. No minimum pitch, via construction or inspection capability is promised by this general guide; feasibility needs a project-specific review.
- SMD land
- A solder-mask-defined land: the mask opening defines the exposed soldering area.
- NSMD land
- A non-solder-mask-defined land: the mask opening clears the copper perimeter.
- Area ratio
- A stencil aperture’s opening area divided by its wall area; one geometric input to paste-release review.
What to resolve before release
Use these review prompts with the actual design, component documentation and agreed manufacturing process.
Verify the ball map and orientation
Check the exact ball or pin numbering, omitted locations, A1/pin-1 marking and top-versus-bottom drawing view. Confirm that the chosen CAD symbol and footprint describe the same package.
Choose the land and mask strategy deliberately
Do not declare NSMD or SMD universally correct. Review the device recommendation, copper geometry and mask-registration constraints together. Fine-pitch QFP leads and exposed-pad QFN packages need different considerations from an area-array package.
Resolve the escape and via construction
Discuss any via inside a solderable land, including its finished surface and the risk of solder loss into an opening. A routing solution is not complete until the fabricator and assembler agree how those features will be manufactured.
Review the stencil with the package mix
Specify aperture shape, foil thickness and exposed-pad printing intentionally. A package-specific recommendation is a starting point for process review, not proof that the complete mixed-component board will print successfully.
Plan the thermal and handling conditions
Collect the device’s moisture and temperature restrictions, board constraints and planned assembly cycles. Qualification peak-temperature information is not a ready-to-use oven recipe; develop the process for the actual assembly.
Agree how hidden joints will be evaluated
Plan inspection and electrical checks before layout release. Define rework access and post-rework evaluation for high-risk sites rather than assuming a hidden joint can be judged from the top of the package.
Different packages, different review questions
Use the exact component drawing and the agreed process as the authority for dimensions and acceptance.
On a small screen, scroll the table horizontally to see every column.
| Package family | Design and process focus | Evidence to request |
|---|---|---|
| BGA / fine-pitch BGA | Ball map, mask strategy, escape vias, coplanarity and local rework access. | Approved footprint and construction; hidden-joint and electrical-test plan. |
| WLCSP / wafer-level package | Device-specific lands, handling, printing and board-level mechanical conditions. | Current device guidance and review of handling and assembly assumptions. |
| QFN / exposed-pad package | Terminal lands, thermal-pad connection, via treatment and paste distribution. | Package drawing and an agreed exposed-pad/stencil design. |
| Fine-pitch QFP / leaded IC | Lead span and tolerance, land geometry, mask and stencil separation. | Footprint-to-package comparison and lead/joint inspection plan. |
| Mixed fine-pitch and large components | Competing paste-volume needs and thermal demands on one assembly. | Documented process strategy and qualification scope for the actual board. |
Keep the approved project requirements in control. Record uncertainties, agreed exceptions and the supporting evidence before the affected operation is released.
Aperture geometry is a calculation—not a pass certificate.
For a straight-walled rectangular aperture, the opening area is L × W and the wall area is 2 × t × (L + W). The calculator below compares those geometric quantities. Actual transfer also depends on the stencil, paste, board support and printing process; no universal pass threshold is applied here.
- Keep the units consistent
- Enter length, width and foil thickness in millimetres.
- Do not confuse volume with deposit
- The geometric aperture volume is not a prediction of transferred paste volume.
- Validate the mixed board
- A suitable geometry for one component may not resolve the needs of all packages.
Rectangular stencil aperture calculator
Straight walls, one rectangular opening. Results describe geometry only.
Input ranges: L/W 0.001–100 mm; t 0.001–10 mm. These broad software limits are not recommended dimensions. No pass/fail threshold is applied.
Move from open questions to controlled decisions.
These steps organize a project review. They do not replace your formal release or acceptance process.
Identify
Confirm package drawing, ball map and orientation.
Co-design
Review routing, lands, mask and via construction.
Develop
Agree printing, handling and thermal conditions.
Verify
Define inspection, test and any rework evidence.
Record the review.
Keep the evidence.
12 checks for this topic. Record status and notes, then export a text copy for your project discussion. A completed checklist is not certification or production approval.
Session only. Nothing is saved automatically or transmitted. Export before closing or reloading. “Reviewed” records evaluation—not a pass verdict. Explain blocked and not-applicable items in the notes.
Showing 12 of 12 checks. Export always includes all checks.
The exact package drawing and revision are identified.
Include package suffix and ball/pin map.
A1 or pin-1 orientation is consistent across files.
Check drawing view conventions.
The footprint matches the actual terminal geometry.
Compare omitted balls, exposed pads and tolerances.
The land and solder-mask strategy is approved.
Do not assume a generic library is sufficient.
Escape routing and via construction are agreed.
Identify any via in a solderable land.
Mask registration and surface requirements are reviewed.
Use the actual fabricator’s confirmed rules.
Apertures and foil thickness are reviewed together.
Include exposed pads and mixed solder-volume needs.
The device’s MSL and thermal limits are available.
Record the permitted handling and process history.
Board support and thermal profiling are planned.
Use representative assembly conditions.
Hidden joints have an agreed evaluation method.
Do not assume a top-side optical image is sufficient.
Electrical tests address the agreed failure risks.
Document what the inspection/test combination does not cover.
Rework access and verification are defined where required.
Review local heating, neighboring parts and subsequent tests.
No checks match these filters. Change a filter to view other items.
Export your checklist and resolve outstanding items with your engineering team before production. Confirm any changes through your normal approval process.
Practical answers
before release.
Use these answers to frame the discussion. The approved project requirements remain the authority for the build.
Is NSMD always the correct choice for a BGA?
No universal choice is made here. Follow the actual package recommendation and review the board fabrication constraints. Do not transfer a land strategy between unrelated package families without evaluation.
Can I put vias directly in BGA or QFN pads?
Only after the via construction and finished solderable surface are agreed. Identify open vias and any proposed fill or cap process explicitly. The package, land size and soldering process determine the required solution.
Does a good stencil area ratio guarantee printing?
No. It describes aperture geometry only. It does not account for the complete paste and printing process, and geometric aperture volume is not a guaranteed deposit volume.
Does X-ray replace electrical testing?
No. An imaging result and an electrical test answer different questions. Define which hidden-joint features are evaluated and which connectivity or functional failures need separate testing.
What void percentage should be accepted?
Use the applicable component, product and contractual acceptance requirements. This guide intentionally supplies no blanket voiding limit: package geometry, measurement method and the governing criteria must be identified.
Technical references & scope
- Texas Instruments — SMT and packaging application notes
Starting point for the application note appropriate to the actual package.
- Analog Devices — QFN PCB design and SMT assembly guidance
Package-specific discussion of pads, paste, thermal lands and inspection; not a universal process recipe.
- Analog Devices — wafer-level package assembly guidance
WLP-specific handling, stencil geometry and assembly considerations. Legacy recommendations require device-level review.
- Texas Instruments — quality, reliability and packaging FAQs
Device-specific MSL, storage and package-temperature information.
- Analog Devices — AN-1448, PBGA rework
Rework planning, thermal characterization and post-rework verification.
- Keysight — Requirement for Successful Boundary Scan Test Development on i1000D In-Circuit Test System (PDF)
Complementary physical and boundary-scan test access.
- IPC Standards — official revision register
Document names, revision history and addendum compatibility; checked 28 September 2026.
Use these engineering references alongside your component documentation and the standards specified for your order. Share your completed checklist with us to confirm assembly, testing and material requirements.