PCB Stackup Reference
Explore layer-order concepts, identify signal references and prepare a stackup that can be approved for manufacture.
Layer count is only the starting point.
A stackup defines the order and construction of the conductive and dielectric layers—not just the number of copper layers.
Electrical performance depends on the signal structure, reference conductors and dielectric geometry. A transmission-line model also needs appropriate material data and finished copper information.
Explore four starting constructions.
These original schematic arrangements illustrate review questions. They are not supplier-standard builds.
4 layers · two signal layers, two ground references
- L1Signal / local powerReference: L2
- L2GroundReference plane
- L3GroundReference plane
- L4Signal / local powerReference: L3
Top to bottom. Pale separators represent dielectrics, not a thickness scale. Solder mask and finish are omitted.
Routing intent
L1 references L2, and L4 references L3. This concept avoids assigning a high-speed outer route to an unspecified split power layer.
Power planning
There is no dedicated power plane. Plan local power pours and routing on the signal layers, then check current, voltage drop and reference clearances.
Review before use
Approve dielectric heights, overall thickness, ground connectivity and layer transitions. A typical board thickness does not imply a typical impedance width.
6 layers · four routing layers with nearby ground
- L1Signal / local powerReference: L2
- L2GroundReference plane
- L3Signal / local powerPrimary reference: L2
- L4Signal / local powerPrimary reference: L5
- L5GroundReference plane
- L6Signal / local powerReference: L5
Top to bottom. Pale separators represent dielectrics, not a thickness scale. Solder mask and finish are omitted.
Routing intent
L1 and L3 use L2 as their designated primary reference; L4 and L6 use L5. The field model must still include all relevant conductors.
Internal-layer spacing
L3 and L4 are adjacent signal layers. Review their separation, routing overlap and coupling; the diagram does not establish an acceptable crosstalk level.
Review before use
This concept has no dedicated power plane. Approve power routing, dielectric separations and return-path transitions before adopting it.
8 layers · four signal layers plus ground and power
- L1SignalReference: L2
- L2GroundReference plane
- L3SignalPrimary reference: L2
- L4PowerAssigned rail / region
- L5PowerAssigned rail / region
- L6SignalPrimary reference: L7
- L7GroundReference plane
- L8SignalReference: L7
Top to bottom. Pale separators represent dielectrics, not a thickness scale. Solder mask and finish are omitted.
Routing intent
L1/L3 are assigned to the L2 ground reference; L6/L8 are assigned to L7. Choose dielectric spacing and model neighboring power copper appropriately.
Power-plane assignment
L4 and L5 are not implicitly the same net. Label every power region, clearance and dielectric isolation requirement. Do not route across a missing designated reference.
Review before use
Check rail distribution, decoupling, interplane behavior and the ground-return connections at signal-layer changes.
10 layers · additional planes around four signal layers
- L1SignalReference: L2
- L2GroundReference plane
- L3SignalPrimary reference: L2
- L4PowerAssigned rail / region
- L5GroundReference / power return
- L6GroundReference / power return
- L7PowerAssigned rail / region
- L8SignalPrimary reference: L9
- L9GroundReference plane
- L10SignalReference: L9
Top to bottom. Pale separators represent dielectrics, not a thickness scale. Solder mask and finish are omitted.
Routing intent
This is a plane-rich example, not a maximum-routing-density example. L1/L3 reference L2, while L8/L10 reference L9.
Construction intent
The mirrored functional arrangement is a starting point. It does not prove mechanical balance: actual dielectric construction and copper distribution still need review.
Review before use
Approve power-ground spacing, ground connections and the complete impedance model. Other ten-layer arrangements may better fit your routing and power needs.
What an approved stackup should contain.
On smaller screens, scroll the table horizontally.
| Item | Record in the approved build | Why the detail matters |
|---|---|---|
| Material | Manufacturer, exact laminate/prepreg grade and permitted substitutions. | Dk and processing behavior cannot be inferred from a broad material label. |
| Dielectrics | Core/prepreg arrangement and finished pressed dielectric thicknesses, with the agreed tolerances. | Prepreg construction and finished spacing must be distinguished. |
| Copper | Base foil specification and finished conductor requirements by layer. | “1 oz” is not an unconditional guarantee of a precise finished copper thickness. |
| Signal references | Signal layers, nearby planes and any relevant coplanar copper or coating. | The impedance model must describe the intended physical structure. |
| Via construction | Through, blind, buried or other specified interconnects, plus fill/cap and backdrill requirements. | These details affect layer access, processing and the finished construction. |
| Acceptance | Finished board thickness, controlled structures, tolerances, coupons and required records. | A coupon represents a defined test structure, not every local feature of every routed net. |
Close the loop between layout and fabrication.
Request a proposed build
Send the board outline, layer count, candidate material, copper needs and electrical targets. Mark the dimensions that are fixed versus adjustable.
Review geometry together
Compare the proposed pressed dielectrics, conductor dimensions and reference layers. Check mechanical balance and practical via construction.
Approve one revision
Release the stackup and impedance table with the same revision as the fabrication package. Record permitted adjustments and required re-approval.
Questions before
you release the design.
Use these answers to clarify the specification, then resolve project-specific requirements with your manufacturing and assembly teams.
Can I copy a stackup from another board?
Use it only as a starting point. Your material, copper, dielectric heights, routing, power distribution and assembly requirements still need review. A copied layer order does not reproduce the original board’s electrical behavior.
Do more layers automatically improve signal integrity?
No. Layer count gives additional construction options, but reference continuity, geometry and routing remain essential. The ten-layer example above is plane-rich; it is not inherently superior for every application.
Can a four-layer board have controlled impedance?
Yes, where the approved geometry and process support the required transmission-line structures. The four-layer concept here does not specify those dimensions or promise a tolerance.
Are these examples electrically and mechanically qualified?
No. They illustrate layer roles and review questions. Final construction, coupling, power integrity, mechanical balance and acceptance requirements must be validated for the project.
Related engineering resources
This page provides conceptual stackup examples for comparing layer and reference-plane arrangements. For guidance specific to a layer count, continue to the detailed stackup guides below.
Technical references
- [1] Polar Instruments — Transmission-line configurations
- [2] Texas Instruments — PCB stackup impact on performance
- [3] Würth Elektronik — Technical Delivery Specification for PCBs (PDF)
- [4] Polar Instruments — Microstrip structures
- [5] Polar Instruments — Stripline structures
- [6] Polar Instruments — Controlled-impedance test coupons
Use these references to compare materials and technical requirements. Confirm the exact grade, construction and applicable documents for your board before ordering.