Stackup & Impedance Design Guide
Connect the electrical target to the actual PCB construction. Define signal layers, reference structures, material assumptions and acceptance requirements before controlled geometry is released.
Start with the electrical requirement. Approve the construction.
A stackup is a manufacturing definition. An impedance target becomes actionable only when it is tied to a physical transmission-line structure.
Identify the interface and the nets that need control. State whether each requirement is single-ended or differential, and use the applicable device and system guidance rather than applying one target to every interface.
Trace width alone does not define impedance. The reference conductors, dielectric and copper geometry all belong in the model.
Use the model that matches the layer structure.
Swipe horizontally to read the full table.
| Structure | Physical arrangement | Inputs that need attention |
|---|---|---|
| Surface microstrip | Outer-layer signal above a reference plane. | Trace-to-plane distance, dielectric, finished conductor shape and any solder-mask coating. |
| Stripline | Internal signal between reference planes. | Both dielectric separations and the reference planes. A centered and an offset trace are different constructions. |
| Edge-coupled differential pair | Two adjacent traces used as a coupled structure. | Width, edge-to-edge pair gap, references and surrounding dielectric. Model the pair rather than treating each conductor independently. |
Put these decisions in the stackup discussion.
Signal and reference layers
Identify a continuous return structure for every controlled group. Review plane gaps and the return connection at each layer transition instead of checking only the visible trace route.
Material and dielectric definition
Record the proposed material system, relevant electrical data and required dielectric separations. State which material substitutions are permitted and which require renewed electrical review.
Finished copper geometry
Separate artwork dimensions from fabricated conductor geometry. Etching and plating affect the finished profile; extra digits in a model do not eliminate physical manufacturing variation.
Mask and neighboring copper
For outer-layer lines, include the intended coating and surrounding conductive features in the model. A coated structure should not silently be calculated as bare microstrip.
Layer count and routing allocation
Assign layer functions before optimizing cost. Check whether the proposed count supports routing access and reference continuity; adding layers without a clear assignment does not finish the electrical design.
Tolerance and permitted changes
Record fixed trace widths or gaps, adjustable dimensions and approval responsibilities. Do not assume that a tight tolerance, material substitution or geometry change is automatically included in a quotation.
Create a table for every controlled structure.
Swipe horizontally to read the full table.
| Required field | Example entry | What to confirm |
|---|---|---|
| Net group & mode | RF path A / single-ended | Identify the actual nets and whether the requirement is single-ended or differential. |
| Target & tolerance | 50 Ω, tolerance to be agreed | The target and allowable variation must come from the project specification, not this example. |
| Signal & reference | L1 signal / L2 reference | Tie the entry to the released stackup and the actual reference geometry. |
| Geometry authority | Width fixed; dielectric proposal requested | State which values are fixed, which may change and who must approve a change. |
| Verification | Representative coupon and agreed report | Specify coverage, measurement method, sampling and the acceptance conditions. |
Copyable handoff worksheet: For each net group, record the design revision; mode and impedance target; allowed tolerance; signal and reference layers; laminate grade; dielectric thickness; finished copper; fixed width/gap; permitted adjustments; coupon structure; measurement/report scope; and approval owner. Leave unknown fields explicitly open for review instead of copying example dimensions.
Convert a percentage tolerance into limits.
Make the acceptance limits readable.
Once your team has selected an allowable percentage, calculate the corresponding lower and upper values. Keep this separate from the engineering decision about which tolerance is appropriate or achievable.
Upper limit = target × (1 + tolerance / 100)
For the illustrative 50 Ω ±10% input, the arithmetic limits are 45 Ω and 55 Ω. A nominal value inside these limits does not, by itself, establish interface compliance.
Impedance tolerance calculator
Default example only. Enable JavaScript for live updates.
This tool does not solve trace width or pair spacing, inspect a stackup, or verify a manufactured board.
Agree what will be measured—and what will not.
Coupon-to-structure mapping
A coupon represents a defined construction fabricated with the panel. Agree which controlled structure each coupon covers; a coupon result is not a direct measurement of every routed net.
Measured construction, not the whole channel
Specify the evidence required for the board and separately define system-level signal-integrity acceptance. Do not use an impedance worksheet as a substitute for a complete interface validation plan.
Report content
Request revision and coupon identity, the target, limits, result and agreed test conditions. Resolve the handling of nonconforming measurements before release rather than after delivery.
Change control
Revisit the agreed model when materials, dielectric heights, copper, coating or routing geometry changes. Keep the final approval record with the released fabrication package.
Frequently asked questions
Check the design, files and manufacturing requirements before sending your next board for production.
What trace width produces 50 Ω?
There is no universal width. The answer depends on the physical structure, dielectric separations and properties, coating and finished copper. Use an appropriate model and an agreed construction.
Is a 100 Ω differential pair always two 50 Ω traces?
No. For a symmetric pair, differential impedance is twice the odd-mode impedance. Coupling means that the impedance of an isolated trace is not necessarily that same odd-mode value.
Does choosing more layers automatically improve the stackup?
No. First define the routing and reference needs, then assign layer functions and review the resulting construction. Layer count is one design choice, not a complete stackup specification.
Does the tolerance calculator solve my routing geometry?
No. It only multiplies the nominal value by the selected percentage to show lower and upper limits. It does not calculate electromagnetic behavior or confirm manufacturability.
Does coupon testing verify every controlled net?
No. The coupon is a separate representative structure. Define any additional product-level or channel-level verification required for your design.
Related engineering resources
Use this guide to prepare the impedance specification. Submit the completed requirements through controlled impedance PCB fabrication review. Review construction examples for 4-layer, 6-layer, 8-layer and 10-layer stackups; confirm the actual design before release.
Technical references & scope notes
- Polar Instruments — Microstrip structures, AP122
- Polar Instruments — Stripline structures, AP123
- Polar Instruments — Modeling precision and fabrication geometry, AP170
- Polar Instruments — Signal-integrity glossary
- Texas Instruments — High-Speed Layout Guidelines, SLLA414A
- Polar Instruments — Controlled-impedance test coupons, AP124
References support general engineering guidance. Supplier-specific limits, example constructions and qualification results are not GlobalWellPCB capabilities. Use the approved project specification and confirmed manufacturing rules for each order. Content reviewed: September 2026.
GlobalWellPCB · Engineering resources
Back to top